you are here: home > products > ant18e specification
This is the specification of the Ant18e logic analyzer module. Additional technical information is presented in the FAQ section.
The Ant18e can be configured as a logic analyzer or as a frequency and event counter.
In logic analyzer mode it operates at up to 1GHz, 18 bits wide, with Asynchronous (Timing) or Synchronous (State) sampling, and Transition sampling. Transition sampling only records data when the inputs change. Slowly changing signals can be sampled at high speed (with corresponding enhanced accuracy) over long periods without running out of acquisition memory space.
In frequency measurement mode it counts frequencies or events simultaneously on all 18 input channels, at frequencies up to 500MHz, and 64-bit event counters on all channels.
Asynchronous (Timing) Sampling |
|
With asynchronous sampling the sampling clock is supplied by the Ant18e. All 18 probes can be assigned as signal inputs. Alternatively, the user can assign 16 probes as signal inputs, one probe as Trigger Out and another probe as Trigger In. |
Synchronous (State) Sampling |
|
With synchronous sampling the sampling clock is supplied by the circuit being tested. The Ant18e captures data at the edges of the incoming clock. It can be set to respond to rising edges, falling edges, or both edges. One probe is Clock In, one probe is Trigger Out, and 16 probes are assigned as signal inputs. |
Acquisition Logic |
|
Asynchronous Sample Rate 1000MHz maximum, 100Hz minimum. Both of the common timing sequences are supported - the 5-2-1 sequence of frequencies (for instance 500MHz, 200MHz, 100MHz) and the 1-2-4 sequence of times (for instance 10ns, 20ns, 40ns) |
|
Synchronous Sample Rate 0 to 100MHz |
|
Acquisition Memory Depth 6K at speeds of 100MHz or less, 8K at higher speeds. Transition sampling compression for repeated samples is up to 256K per acquisition memory slot. |
|
Threshold 0.8V to 2.5V, in steps of 0.1V |
|
Minimum Input 0.5V below threshold for Lo, 0.5V above threshold for Hi |
|
Trigger Connections Trigger In and Trigger Out. |
|
Input Skew less than 2ns, channel to channel |
|
Input Impedance 100Kohms in parallel with 10pF |
|
Maximum Input Voltages +/-40V DC, +/-15V AC |
Triggering |
|
Conditions 0, 1, Rising Edge, Falling Edge, Either Edge, and DON'T CARE for all channels |
|
Pattern Recognisers 2 |
|
Edges Trigger on the condition becoming TRUE or on the condition becoming FALSE |
|
Pass Count 0 to 1023 |
|
Trigger Logic Multi-state trigger logic with Edge, Pattern, and Complex triggering. Complex triggering includes occurrence counting and minimum and maximum duration measurement |
|
Trigger Position 10% to 90% of acquisition memory, in 10% steps |
Frequency Measurement and Event Counting |
|
Channels 18 |
|
Channel Thresholds The same variable threshold as for the logic analyzer function |
|
Frequency Range 500MHz down to less than 0.01Hz |
|
Digits 19 (64 bits) |
|
Accuracy +/-0.01% |
|
Frequency Measuring Method Direct and Reciprocal Counting |
|
Internal Gate Time 100ms, 1s, 10s, or infinite |
|
External Gating for Event Counting Optionally gated (enabled) by a pattern match on any or all of the lower 8 logic analyzer channels |
Environmental |
|
Operating Temperature 5°C to 40°C |
|
Storage Temperature -40°C to 75°C |
|
Size 65 mm x 35mm x 15mm (2.5" x 1.4" x 0.6") |
|
Power Consumption 2.2W maximum |
|
Power Source Via USB cable. No external power supply |
|
Computer Connection USB connection to computer. Includes an attached USB cable |
Software Features |
|
Host Computer Logic Analyzer front panel software included for Windows 98/ME/2000/XP |
|
Print Waveforms Yes |
|
Data Output Text File and CSV File |
|
Cursors 1 main cursor plus 1 auxiliary cursor |
|
User-Level Programming Library Yes |